Projects per year
Personal profile
Expertise related to UN Sustainable Devlopment Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Dive into the research topics where Ramesh Harjani is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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ALIGN: Analog Layout, Intelligently Generated from Netlists
Sapatnekar, S. S. & Harjani, R.
8/13/18 → 8/12/21
Project: Research project
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U-Fast Hoppor: Ultra-Fast Hopping Orthogonal frequency c
USDOD DEFENSE ADV RES PROJECTS
10/27/16 → 8/18/20
Project: Research project
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Digital Yet Deliberately Random -- Synthesizing Logical
Riedel, M., Bazargan, K., Harjani, R. & Lilja, D. J.
7/1/12 → 6/30/15
Project: Research project
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6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB
Poojary, J. & Harjani, R., Feb 13 2021, 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. 96-98 3 p. 9365973. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 64).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Aging of Current DACs and its Impact in Equalizer Circuits
Dhar, T., Poojary, J., Harjani, R. & Sapatnekar, S. S., Mar 2021, 2021 IEEE International Reliability Physics Symposium, IRPS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9405160. (IEEE International Reliability Physics Symposium Proceedings; vol. 2021-March).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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ALIGN: A System for Automating Analog Layout
Dhar, T., Kunal, K., Li, Y., Madhusudan, M., Poojary, J., Sharma, A. K., Xu, W., Burns, S. M., Harjani, R., Hu, J., Kirkpatrick, D. A., Mukherjee, P., Yaldiz, S. & Sapatnekar, S. S., Apr 2021, In: IEEE Design and Test. 38, 2, p. 8-18 11 p., 9279310.Research output: Contribution to journal › Article › peer-review
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SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers
Harjani, R., Chen, M., Berkhout, M., Vanderhaegan, J., Lee, T. H., Staszewski, R. B., Philips, K., Luong, H. C. & Ivanov, V., Feb 13 2021, In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 64, p. 541-542 2 p., 9365991.Research output: Contribution to journal › Editorial › peer-review
Open Access -
A Customized Graph Neural Network Model for Guiding Analog IC Placement
Li, Y., Lin, Y., Madhusudan, M., Sharma, A., Xu, W., Sapatnekar, S. S., Harjani, R. & Hu, J., Nov 2 2020, In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2020-November, 9256781.Research output: Contribution to journal › Conference article › peer-review
Open Access