A 2 μW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.
Bibliographical noteFunding Information:
Manuscript received June 10, 2007; revised October 3, 2007. This work was supported by Intel, IBM, and United Microelectronics Corporation (UMC). The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: thkim@umn. edu). Digital Object Identifier 10.1109/JSSC.2007.914328
Copyright 2008 Elsevier B.V., All rights reserved.
- Low-voltage memory
- Reverse short channel effect
- Subthreshold SRAM
- Voltage scaling