A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Ki Chul Chun; Pulkit Jain; Tae Ho Kim; Chris H. Kim

doi:10.1109/VLSIC.2010.5560303

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

Ki Chul Chun, Pulkit Jain, Tae Ho Kim, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Scopus citations

Abstract

A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

Original language	English (US)
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Pages	191-192
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560303
State	Published - Oct 22 2010
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: Jun 16 2010 → Jun 18 2010

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/Territory	United States
City	Honolulu, HI
Period	6/16/10 → 6/18/10

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title = "A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec",

abstract = "A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.",

author = "Chun, {Ki Chul} and Pulkit Jain and Kim, {Tae Ho} and Kim, {Chris H.}",

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AU - Jain, Pulkit

AU - Kim, Tae Ho

AU - Kim, Chris H.

PY - 2010/10/22

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N2 - A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

AB - A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

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BT - 2010 Symposium on VLSI Circuits, VLSIC 2010

T2 - 2010 24th Symposium on VLSI Circuits, VLSIC 2010

Y2 - 16 June 2010 through 18 June 2010

ER -

A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

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