A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

J. O. Plouchart; M. Ferriss; A. Natarajan; A. Valdes-Garcia; B. Sadhu; A. Rylyakov; B. Parker; M. Beakes; A. Babakani; S. Yaldiz; L. Pileggi; Ramesh Harjani; S. Reynolds; J. A. Tierno; D. Friedman

doi:10.1109/CICC.2012.6330593

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

J. O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, Ramesh Harjani, S. Reynolds, J. A. Tierno, D. Friedman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs	https://doi.org/10.1109/CICC.2012.6330593
State	Published - 2012
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States Duration: Sep 9 2012 → Sep 12 2012

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Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

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Other	34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/Territory	United States
City	San Jose, CA
Period	9/9/12 → 9/12/12

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10.1109/CICC.2012.6330593

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Plouchart, J. O., Ferriss, M., Natarajan, A., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B., Beakes, M., Babakani, A., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., & Friedman, D. (2012). A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 Article 6330593 (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330593

Plouchart, JO, Ferriss, M, Natarajan, A, Valdes-Garcia, A, Sadhu, B, Rylyakov, A, Parker, B, Beakes, M, Babakani, A, Yaldiz, S, Pileggi, L, Harjani, R, Reynolds, S, Tierno, JA & Friedman, D 2012, A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012., 6330593, Proceedings of the Custom Integrated Circuits Conference, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 9/9/12. https://doi.org/10.1109/CICC.2012.6330593

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title = "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS",

abstract = "A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.",

author = "Plouchart, {J. O.} and M. Ferriss and A. Natarajan and A. Valdes-Garcia and B. Sadhu and A. Rylyakov and B. Parker and M. Beakes and A. Babakani and S. Yaldiz and L. Pileggi and Ramesh Harjani and S. Reynolds and Tierno, {J. A.} and D. Friedman",

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AU - Sadhu, B.

AU - Rylyakov, A.

AU - Parker, B.

AU - Beakes, M.

AU - Babakani, A.

AU - Yaldiz, S.

AU - Pileggi, L.

AU - Harjani, Ramesh

AU - Reynolds, S.

AU - Tierno, J. A.

AU - Friedman, D.

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

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