A 54 Mbps (3,6)-regular FPGA LDPC decoder

Tong Zhang; K. K. Parhi

doi:10.1109/SIPS.2002.1049697

A 54 Mbps (3,6)-regular FPGA LDPC decoder

Tong Zhang, K. K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

87 Scopus citations

Abstract

Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10^-6 at 2 dB over an AWGN channel.

Original language	English (US)
Title of host publication	IEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publication	Design and Implementation
Pages	127-132
Number of pages	6
ISBN (Electronic)	0780375874
DOIs	https://doi.org/10.1109/SIPS.2002.1049697
State	Published - 2002

Keywords

AWGN channels
Application specific integrated circuits
Bit error rate
Design methodology
Field programmable gate arrays
Hardware
Iterative decoding
Parity check codes
Routing
Throughput

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A 54 Mbps (3,6)-regular FPGA LDPC decoder

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Keywords

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