A BiCMOS implementation of a 276MS/s forward equalizer and 200MS/s FDTS detector

R. Harjani, R. Barnett, M. Butenhoff

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

An analog finite impulse response filter (FIR) and an analog fixed delay tree search (FDTS) tau=1 detector suitable for disk drive applications are presented. The FIR uses a rotary architecture with interleaved operation which allows clock rates up to 276MS/S to be used. The FIR has seven taps, all programmable to six bit weights, and is implemented in fully differential form. The detector operates with clock rates up to 200MS/s with no code restrictions. It makes use of a reduced minimum mean square error equation set to simplify the detector. Dual feedback filters are also used to shorten the critical path. A seven tap feedback filter is used with six bits of resolution per tap. The FIR consumes 180 mW while the detector uses 270 mW. The die size including all test buffers for the FIR and detector is 5.2 mm2.

Original languageEnglish (US)
Pages (from-to)160-165
Number of pages6
JournalIEEE Transactions on Magnetics
Volume34
Issue number1 PART 1
StatePublished - Dec 1 1998

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