TY - GEN
T1 - A chip-level electrostatic discharge simulation strategy
AU - Qian, Haifeng
AU - Kozhaya, Joseph N.
AU - Nassif, Sani R.
AU - Sapatnekar, Sachin S
PY - 2004/12/1
Y1 - 2004/12/1
N2 - This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V DD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.
AB - This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V DD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.
UR - http://www.scopus.com/inward/record.url?scp=16244379545&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=16244379545&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2004.1382593
DO - 10.1109/ICCAD.2004.1382593
M3 - Conference contribution
AN - SCOPUS:16244379545
SN - 0780387023
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 315
EP - 318
BT - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Y2 - 7 November 2004 through 11 November 2004
ER -