Abstract
Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs.
Original language | English (US) |
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Article number | 6918412 |
Pages (from-to) | 3737-3743 |
Number of pages | 7 |
Journal | IEEE Transactions on Electron Devices |
Volume | 61 |
Issue number | 11 |
DOIs | |
State | Published - Nov 1 2014 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
Keywords
- Embedded flash (eFlash) memory
- embedded nonvolatile memory (eNVM)
- single-poly eFlash.