A compiler framework for general memory layout optimizations targeting structures

Jin Lin, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents a novel approach which integrates both structure layout optimization and array flattening in a unified compiler framework to improve memory locality and reduce required memory bandwidth. The proposed compiler framework includes alias group-wise safety analysis, memory layout profitability analysis and memory layout transformations. The alias group-wise safety analysis is proposed to process the candidates of structure layout optimization and array flattening in a unified framework. The alias group-wise approach could expose more opportunities for structure layout optimization and array flattening. The profitability analysis including array dimension reordering and structure layout profitability analysis tries to select a profitable data layout that enables more structure layout optimizations as well as array flattening to exploit more data locality. Experimental results show that the implemented framework delivers significant performance gain for memory intensive programs in CPU2006 and OMP2001 suites.

Original languageEnglish (US)
Title of host publicationINTERACT-14 - Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
DOIs
StatePublished - May 18 2010
Event2010 Workshop on Interaction between Compilers and Computer Architecture, INTERACT-14 - Pittsburgh, PA, United States
Duration: Mar 13 2010Mar 13 2010

Publication series

NameProceedings - Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT
ISSN (Print)1550-6207

Conference

Conference2010 Workshop on Interaction between Compilers and Computer Architecture, INTERACT-14
CountryUnited States
CityPittsburgh, PA
Period3/13/103/13/10

Keywords

  • Array flattening
  • Structure layout optimization

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