A convex optimization approach to transistor sizing for CMOS circuits

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

The transistor sizing problem of minimizing the circuit area, subject to the circuit delay being less than a given specification, is formulated as a convex programming problem. An efficient convex programming algorithm is then used to obtain the exact solution. Experimental results on a variety of circuits show that, for a given delay specification, this approach is able to produce circuits with significantly smaller area when compared with TILOS.

Original languageEnglish (US)
Title of host publication1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
PublisherPubl by IEEE
Pages482-485
Number of pages4
ISBN (Print)0818621575
StatePublished - Dec 1 1992
Event1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
Duration: Nov 11 1991Nov 14 1991

Other

Other1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
CitySanta Clara, CA, USA
Period11/11/9111/14/91

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