A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations

Chris H. Kim, Jae Joon Kim, Saibal Mukhopadhyay, Kaushik Roy

Research output: Contribution to journalConference articlepeer-review

43 Scopus citations

Abstract

This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high VT (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieve by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high V T device, the 2-D halo doping profile was optimized considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.

Original languageEnglish (US)
Pages (from-to)6-9
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 1 2003
EventProceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

Keywords

  • Forward body-biasing
  • Leakage power
  • SRAM
  • Super high V

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