TY - GEN
T1 - A generalized and unified SPFD-based rewiring technique
AU - Maidee, Pongstorn
AU - Bazargan, Kia
PY - 2007
Y1 - 2007
N2 - Traditionally, logic synthesis constrains the solution space of later design steps, such as physical design, because they are applied in sequence. Rewiring is a technique to restructure a circuit while maintaining its functionality. Since design properties and objectives can be considered during post-synthesis rewiring, it can help relieve constraints put forth by decisions made at earlier design steps. The extent of rewiring of a rewiring algorithm has a great impact on the success of the design flow. This paper presents a powerful rewiring technique that in addition to unifying all previously proposed Set-of-Pairs-of-Functions-to-be-Distinguished based rewiring techniques, it can perform rewiring with more than one wire which increases our ability to circumvent poorly-decided early design constraints. With this ability, the rewiring ability of using different numbers of wires is reported for the first time in this paper. Our technique can be used for run-time/quality trade-off in any given rewiring application.
AB - Traditionally, logic synthesis constrains the solution space of later design steps, such as physical design, because they are applied in sequence. Rewiring is a technique to restructure a circuit while maintaining its functionality. Since design properties and objectives can be considered during post-synthesis rewiring, it can help relieve constraints put forth by decisions made at earlier design steps. The extent of rewiring of a rewiring algorithm has a great impact on the success of the design flow. This paper presents a powerful rewiring technique that in addition to unifying all previously proposed Set-of-Pairs-of-Functions-to-be-Distinguished based rewiring techniques, it can perform rewiring with more than one wire which increases our ability to circumvent poorly-decided early design constraints. With this ability, the rewiring ability of using different numbers of wires is reported for the first time in this paper. Our technique can be used for run-time/quality trade-off in any given rewiring application.
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U2 - 10.1109/FPL.2007.4380664
DO - 10.1109/FPL.2007.4380664
M3 - Conference contribution
AN - SCOPUS:48149113104
SN - 1424410606
SN - 9781424410606
T3 - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
SP - 305
EP - 310
BT - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 27 August 2007 through 29 August 2007
ER -