Abstract
Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-μm CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1895-1900 |
| Number of pages | 6 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 40 |
| Issue number | 9 |
| DOIs | |
| State | Published - Sep 2005 |
Bibliographical note
Funding Information:Manuscript received November 16, 2004; revised Febuary 18, 2005. This work was supported in part by Bermai, Inc. Y. Ding is with Silicon Laboratories, Inc., Austin, TX 78745 USA (e-mail: yongwang.ding@silabs.com). R. Harjani is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: harjani@ ece.umn.edu). Digital Object Identifier 10.1109/JSSC.2005.848179
Keywords
- CMOS
- Class A
- Class AB
- Power amplifier