A high-efficiency CMOS +22-dBm linear power amplifier

Yongwang Ding, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

38 Scopus citations


Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-μm CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.

Original languageEnglish (US)
Pages (from-to)1895-1900
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number9
StatePublished - Sep 1 2005


  • CMOS
  • Class A
  • Class AB
  • Power amplifier

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