A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis

Qichen Zhang; Yun Chen; Shixian Li; Xiaoyang Zeng; Keshab K. Parhi

doi:10.1109/TCSI.2020.3003457

A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis

Qichen Zhang, Yun Chen, Shixian Li, Xiaoyang Zeng, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

This paper presents an area-efficient architecture for stochastic low-density parity-check (LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The correlation effects of a stochastic Sum-Product Algorithm (SPA) are analyzed. Based on this analysis, a variable node (VN) structure is proposed and its similarity with a correlation divider (CORDIV) is pointed out. Based on the properties of CORDIV, the area of probability tracer in the VN is reduced significantly. In order to achieve more accurate results when the check-to-variable (C2V) messages are not strong enough, the 3-3 input grouping sub-node is replaced by an adder-based 5-1 input grouping sub-node of the degree-6 VN for (2048,1723) code. An unbiased stochastic sequence generator is adopted to get more accurate results from the smaller probability tracer. Furthermore, the soft bit-flipping prior-processing and the C2V-based hard decision updating method are combined in VN to reduce the decoding latency. A (2048,1723) stochastic LDPC decoder is designed in the TSMC 65 nm process to demonstrate the proposed decoder architecture. With the aid of early termination, the decoder occupies 2.34 mm2 core area and can achieve 116.17 Gb/s at 4.4 dB and 461.99 Gb/s at 5.5 dB under 970 MHz with better decoding performance. Compared with the state-of-the-art stochastic IEEE 802.3an LDPC decoders, the proposed architecture can achieve the best throughput, throughput-to-area ratio, and BER performance.

Original language	English (US)
Article number	9126828
Pages (from-to)	5429-5442
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	67
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2020.3003457
State	Published - Dec 2020

Bibliographical note

Funding Information:
This work was supported in part by the National Natural Science Foundation of China under Grant 61525401 and Grant 61774049, and in part by the National Key Research and Development Programmes under Grant 2018YFB2201000.

Funding Information:
Manuscript received January 20, 2020; revised April 9, 2020; accepted June 11, 2020. Date of publication June 26, 2020; date of current version December 1, 2020. This work was supported in part by the National Natural Science Foundation of China under Grant 61525401 and Grant 61774049, and in part by the National Key Research and Development Programmes under Grant 2018YFB2201000. This article was recommended by Associate Editor I. Kale. (Corresponding author: Yun Chen.) Qichen Zhang, Yun Chen, Shixian Li, and Xiaoyang Zeng are with the State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China (e-mail: qczhang16@fudan.edu.cn; chenyun@fudan.edu.cn; shixianli17@fudan.edu.cn; xyzeng@fudan.edu.cn).

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

IEEE 802.3an
Low-density parity-check
correlation
stochastic decoder
variable node

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@article{8329061426bf41ecb497483c02c2e12e,

title = "A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis",

abstract = "This paper presents an area-efficient architecture for stochastic low-density parity-check (LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The correlation effects of a stochastic Sum-Product Algorithm (SPA) are analyzed. Based on this analysis, a variable node (VN) structure is proposed and its similarity with a correlation divider (CORDIV) is pointed out. Based on the properties of CORDIV, the area of probability tracer in the VN is reduced significantly. In order to achieve more accurate results when the check-to-variable (C2V) messages are not strong enough, the 3-3 input grouping sub-node is replaced by an adder-based 5-1 input grouping sub-node of the degree-6 VN for (2048,1723) code. An unbiased stochastic sequence generator is adopted to get more accurate results from the smaller probability tracer. Furthermore, the soft bit-flipping prior-processing and the C2V-based hard decision updating method are combined in VN to reduce the decoding latency. A (2048,1723) stochastic LDPC decoder is designed in the TSMC 65 nm process to demonstrate the proposed decoder architecture. With the aid of early termination, the decoder occupies 2.34 mm2 core area and can achieve 116.17 Gb/s at 4.4 dB and 461.99 Gb/s at 5.5 dB under 970 MHz with better decoding performance. Compared with the state-of-the-art stochastic IEEE 802.3an LDPC decoders, the proposed architecture can achieve the best throughput, throughput-to-area ratio, and BER performance. ",

keywords = "IEEE 802.3an, Low-density parity-check, correlation, stochastic decoder, variable node",

author = "Qichen Zhang and Yun Chen and Shixian Li and Xiaoyang Zeng and Parhi, {Keshab K.}",

note = "Funding Information: This work was supported in part by the National Natural Science Foundation of China under Grant 61525401 and Grant 61774049, and in part by the National Key Research and Development Programmes under Grant 2018YFB2201000. Funding Information: Manuscript received January 20, 2020; revised April 9, 2020; accepted June 11, 2020. Date of publication June 26, 2020; date of current version December 1, 2020. This work was supported in part by the National Natural Science Foundation of China under Grant 61525401 and Grant 61774049, and in part by the National Key Research and Development Programmes under Grant 2018YFB2201000. This article was recommended by Associate Editor I. Kale. (Corresponding author: Yun Chen.) Qichen Zhang, Yun Chen, Shixian Li, and Xiaoyang Zeng are with the State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China (e-mail: qczhang16@fudan.edu.cn; chenyun@fudan.edu.cn; shixianli17@fudan.edu.cn; xyzeng@fudan.edu.cn). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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N2 - This paper presents an area-efficient architecture for stochastic low-density parity-check (LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The correlation effects of a stochastic Sum-Product Algorithm (SPA) are analyzed. Based on this analysis, a variable node (VN) structure is proposed and its similarity with a correlation divider (CORDIV) is pointed out. Based on the properties of CORDIV, the area of probability tracer in the VN is reduced significantly. In order to achieve more accurate results when the check-to-variable (C2V) messages are not strong enough, the 3-3 input grouping sub-node is replaced by an adder-based 5-1 input grouping sub-node of the degree-6 VN for (2048,1723) code. An unbiased stochastic sequence generator is adopted to get more accurate results from the smaller probability tracer. Furthermore, the soft bit-flipping prior-processing and the C2V-based hard decision updating method are combined in VN to reduce the decoding latency. A (2048,1723) stochastic LDPC decoder is designed in the TSMC 65 nm process to demonstrate the proposed decoder architecture. With the aid of early termination, the decoder occupies 2.34 mm2 core area and can achieve 116.17 Gb/s at 4.4 dB and 461.99 Gb/s at 5.5 dB under 970 MHz with better decoding performance. Compared with the state-of-the-art stochastic IEEE 802.3an LDPC decoders, the proposed architecture can achieve the best throughput, throughput-to-area ratio, and BER performance.

AB - This paper presents an area-efficient architecture for stochastic low-density parity-check (LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The correlation effects of a stochastic Sum-Product Algorithm (SPA) are analyzed. Based on this analysis, a variable node (VN) structure is proposed and its similarity with a correlation divider (CORDIV) is pointed out. Based on the properties of CORDIV, the area of probability tracer in the VN is reduced significantly. In order to achieve more accurate results when the check-to-variable (C2V) messages are not strong enough, the 3-3 input grouping sub-node is replaced by an adder-based 5-1 input grouping sub-node of the degree-6 VN for (2048,1723) code. An unbiased stochastic sequence generator is adopted to get more accurate results from the smaller probability tracer. Furthermore, the soft bit-flipping prior-processing and the C2V-based hard decision updating method are combined in VN to reduce the decoding latency. A (2048,1723) stochastic LDPC decoder is designed in the TSMC 65 nm process to demonstrate the proposed decoder architecture. With the aid of early termination, the decoder occupies 2.34 mm2 core area and can achieve 116.17 Gb/s at 4.4 dB and 461.99 Gb/s at 5.5 dB under 970 MHz with better decoding performance. Compared with the state-of-the-art stochastic IEEE 802.3an LDPC decoders, the proposed architecture can achieve the best throughput, throughput-to-area ratio, and BER performance.

KW - IEEE 802.3an

KW - Low-density parity-check

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KW - stochastic decoder

KW - variable node

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A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis

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