A high-speed architecture for ADPCM codec

Naresh R. Shanbhag, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of relaxed form of look-ahead. The hardware overhead is only the the pipelining latches and is independent of the number of quantizer levels, the predictor order and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with that of the serial one. Speech and image coding examples are presented to support the conclusions in this paper.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1499-1502
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

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