A jitter-resilient sampling technique for high-resolution ADCs in wideband RF receivers

In this paper, we analyze a novel sampling technique that addresses the clock jitter problem in high resolution wideband ADCs. The proposed sampler shapes the jitter-induced error in a manner similar to a ΔΣ ADC, which normally shapes the quantization noise. The clock jitter at the sampler is suppressed by the loop filter, and the impact of feedback pulse jitter is reduced through use of switched-capacitor feedback. As opposed to prior studies, we show that the a ΔΣ sampler suppresses the jitter error by more than 10X even at low OSR. As an example, a 2nd-order ΔΣ sampler increases the SJNR by 22 dB at OSR=5, corresponding to more than 3-bit improvement in the achievable SNR. Analysis indicates that increasing the loop order and/or OSR improves the amount of jitter suppression. In addition, the ΔΣ sampler provides the clock programmable anti-aliasing properties of an integration sampler. The analysis was validated via macro-model simulations in MATLAB and circuit simulation in Cadence.