A low complexity floating-point complex multiplier with a three-term dot-product unit

Sangho Yun, Gerald E. Sobelman, Xiaofang Zhou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper, we propose a new design for a low complexity floating-point complex multiplier for DSP applications. The design uses a three-term dot-product unit that reduces the overlapped portion found in a previous two-term fused dot-product unit. Comparisons with a primitive fused adder-subtract unit, a dot-product unit and combinations of these primitive units have also been performed. The synthesis results using a 45-nm standard-cell library shows a 16% reduction in area and a 6% reduction in power consumption as compared to a previous complex multiplier using two fused dot-product units.

Original languageEnglish (US)
Title of host publication2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages549-552
Number of pages4
ISBN (Electronic)9781479952748
DOIs
StatePublished - Dec 15 2014
Event2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014 - Guilin, Guangxi, China
Duration: Aug 5 2014Aug 8 2014

Publication series

Name2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014

Other

Other2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014
CountryChina
CityGuilin, Guangxi
Period8/5/148/8/14

Keywords

  • Floating-point complex multiplier
  • fused add-subtract
  • fused dot product
  • three-term fused dot product

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