A mixed functional/IDDQ testing methodology for CMOS transistor faults

E. Vandris, G. Sobelman

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A fault preprocessing procedure that determines the detectability of transistor faults is presented, and examples are given for static and dynamic CMOS logic. The fault simulation procedure is presented for both logic and IDDQ testing. Simulation results for typical circuits are also presented.

Original languageEnglish (US)
Pages (from-to)608-614
Number of pages7
JournalDigest of Papers - International Test Conference
StatePublished - Jan 1 1992

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