A mixed functional/IDDQ testing methodology for CMOS transistor faults

E. Vandris; G. Sobelman

A mixed functional/IDDQ testing methodology for CMOS transistor faults

E. Vandris, G. Sobelman

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A fault preprocessing procedure that determines the detectability of transistor faults is presented, and examples are given for static and dynamic CMOS logic. The fault simulation procedure is presented for both logic and I_DDQ testing. Simulation results for typical circuits are also presented.

Original language	English (US)
Pages (from-to)	608-614
Number of pages	7
Journal	Digest of Papers - International Test Conference
State	Published - Jan 1 1992

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A mixed functional/IDDQ testing methodology for CMOS transistor faults

Abstract

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