A new approach to the use of satisfiability in false path detection

Felipe S. Marques; Renato P. Ribas; Sachin Sapatnekar; André I. Reis

doi:10.1145/1057661.1057735

A new approach to the use of satisfiability in false path detection

Felipe S. Marques, Renato P. Ribas, Sachin Sapatnekar, André I. Reis

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

6 Scopus citations

Abstract

This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

Original language	English (US)
Pages	308-311
Number of pages	4
DOIs	https://doi.org/10.1145/1057661.1057735
State	Published - 2005
Event	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States Duration: Apr 17 2005 → Apr 19 2005

Other

Other	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
Country/Territory	United States
City	Chicago, IL
Period	4/17/05 → 4/19/05

Keywords

False Paths
Satisfiability
Unateness

Access

10.1145/1057661.1057735

OpenUrl availability

Full text

Cite this

@conference{f4301e4fab38411f9bfc657fcad5264d,

title = "A new approach to the use of satisfiability in false path detection",

abstract = "This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.",

keywords = "False Paths, Satisfiability, Unateness",

author = "Marques, {Felipe S.} and Ribas, {Renato P.} and Sachin Sapatnekar and Reis, {Andr{\'e} I.}",

year = "2005",

doi = "10.1145/1057661.1057735",

language = "English (US)",

pages = "308--311",

}

TY - CONF

T1 - A new approach to the use of satisfiability in false path detection

AU - Marques, Felipe S.

AU - Ribas, Renato P.

AU - Sapatnekar, Sachin

AU - Reis, André I.

PY - 2005

Y1 - 2005

N2 - This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

AB - This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

KW - False Paths

KW - Satisfiability

KW - Unateness

UR - http://www.scopus.com/inward/record.url?scp=29244444231&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=29244444231&partnerID=8YFLogxK

U2 - 10.1145/1057661.1057735

DO - 10.1145/1057661.1057735

M3 - Paper

AN - SCOPUS:29244444231

SP - 308

EP - 311

T2 - 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05

Y2 - 17 April 2005 through 19 April 2005

ER -

A new approach to the use of satisfiability in false path detection

Abstract

Other

Keywords

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this