Abstract
Abstract-This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. Since the delay under this model is a convex function, optimal sizing algorithms based on convex programming techniques are applied with the new delay model. Experimental results demonstrating the accuracy of proposed model are presented along with results of sizing various test circuits.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 779-788 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 19 |
| Issue number | 7 |
| DOIs | |
| State | Published - 2000 |
Bibliographical note
Funding Information:Manuscript received August 31, 1998; revised January 12, 2000. This work is supported in part by a gift from Intel Corporation, by the National Science Foundation (NSF) under contract CCR-9800992, and by the Semiconductor Research Corporation (SRC) under contract 98-DJ-609. This paper was recommended by Associate Editor M. Pedram The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 0278-0070(00)05858-9.