A new reconfigurable bit-serial systolic divider for GF(2M) and GF(P)

Aaron E. Cohen; Keshab K. Parhi

doi:10.1109/ICASSP.2005.1416251

A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P)

Aaron E. Cohen, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper focuses on the design of a new dual field divider that can achieve performance of 1/m throughput. This dual field division unit can operate at 118 MHz with a latency of 7m - 2 cycles and has an area requirement 15 XOR2, 40 AND2, 29 MUX2, and 7 INV gates per processing element with a total of 2m processing elements. It is intended to be used in an Elliptic Curve Crypto-Accelerator for GF(2^m) and GF(_p). The actual performance for scalar point multiplication in GF(2⁵⁷¹) running at 100 MHz would be 20.4 kP/s. The actual performance for scalar point multiplication in GF(p) with |p| = 521 running at 100 MHz would be 24.4 kP/s.

Original language	English (US)
Title of host publication	2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	V105-V108
ISBN (Print)	0780388747, 9780780388741
DOIs	https://doi.org/10.1109/ICASSP.2005.1416251
State	Published - Jan 1 2005
Event	2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05 - Philadelphia, PA, United States Duration: Mar 18 2005 → Mar 23 2005

Publication series

Name	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	V
ISSN (Print)	1520-6149

Other

Other	2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05
Country/Territory	United States
City	Philadelphia, PA
Period	3/18/05 → 3/23/05

Access

10.1109/ICASSP.2005.1416251

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Cite this

Cohen, A. E., & Parhi, K. K. (2005). A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P). In 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions (pp. V105-V108). Article 1416251 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; Vol. V). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASSP.2005.1416251

A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P). / Cohen, Aaron E.; Parhi, Keshab K.
2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions. Institute of Electrical and Electronics Engineers Inc., 2005. p. V105-V108 1416251 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; Vol. V).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cohen, AE & Parhi, KK 2005, A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P). in 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions., 1416251, ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, vol. V, Institute of Electrical and Electronics Engineers Inc., pp. V105-V108, 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05, Philadelphia, PA, United States, 3/18/05. https://doi.org/10.1109/ICASSP.2005.1416251

Cohen AE, Parhi KK. A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P). In 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions. Institute of Electrical and Electronics Engineers Inc. 2005. p. V105-V108. 1416251. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings). doi: 10.1109/ICASSP.2005.1416251

Cohen, Aaron E. ; Parhi, Keshab K. / A new reconfigurable bit-serial systolic divider for GF(2^M) and GF(P). 2005 IEEE ICASSP '05 - Proc. - Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions. Institute of Electrical and Electronics Engineers Inc., 2005. pp. V105-V108 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings).

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