A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs

Wei Ting Loke, Yajun Ha, Wenfeng Zhao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric VT through RBB offer the potential of reducing leakage power with minimal or no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs deploy a similar strategy, but with optimizations limited to the post-P&R stage. We present a novel two-stage technology mapping (RBBMap) and logic block packing (RBBPack) tool that is free from clustering constraints limiting the post-P&R method, and moves RBB optimizations upwards to the technology mapping level. Using the baseline technology mapping tool Emap, our tools generate an average of 70.95% savings in logic block leakage power and 28.30% savings in total energy consumption.

Original languageEnglish (US)
Title of host publicationProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Pages221-226
Number of pages6
DOIs
StatePublished - Oct 18 2012
Event2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012 - Shanghai, China
Duration: May 21 2012May 25 2012

Publication series

NameProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Other

Other2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
CountryChina
CityShanghai
Period5/21/125/25/12

Keywords

  • Dual-VT
  • EDA
  • FPGA
  • Programmable-VT
  • Reverse Back Bias
  • Technology Mapping

Fingerprint

Dive into the research topics of 'A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs'. Together they form a unique fingerprint.

Cite this