A power efficient frequency shaping neural recorder with automatic bandwidth adjustment

Jian Xu, Tong Wu, Zhi Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents a frequency-shaping (FS) neural recorder with automatic bandwidth adjustment. The proposed recorder inherently attenuates electrode offset and motion artifacts, compresses neural data dynamic range by 4.5-bit, and achieves a 3 pF input impedance to better support chronic recording experiments. A major drawback of an FS recorder is larger input referred noise due to noise aliasing and reduced gain at low frequencies. In this work, we have proposed a multi-phase sampling and processing technique which can 10 times reduce the noise. In addition, a neural spike processor operating at a low duty cycle has been integrated, where the processing results are feedback to the analog frontend: when the channel contains no/little spike activities, the recorder bandwidth is automatically reduced to record local field potentials (LFPs) only. The bandwidth reduction enables substantial power saving for that channel (4 times in the current implementation). The bandwidth is then automatically restored back to 8 kHz once spikes are detected from the spiking probability map. A prototyping chip has been fabricated in a 0.13 μm CMOS process. When measured at a 80 kHz sampling clock and 1.0 V supply, the recorder achieves a 3 pF input capacitance, 2.2 μV input noise for recording spikes, and 15 μW/ch power for amplifiers, filters, multiplexer, analog-to-digital converter (ADC), and digital filters combined. Empirical studies on in-vivo recordings from monkeys show that over 70% of channels do not contain detectable spikes, suggesting an averaged recording power reduction by 50% to 7.5 μW/ch.

Original languageEnglish (US)
Title of host publication2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages197-200
Number of pages4
ISBN (Electronic)9781479940905
DOIs
StatePublished - Jan 13 2015
Event2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan, Province of China
Duration: Nov 10 2014Nov 12 2014

Publication series

Name2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/TerritoryTaiwan, Province of China
CityKaohsiung
Period11/10/1411/12/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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