Abstract
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology mapping.
Original language | English (US) |
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Pages | 210-217 |
Number of pages | 8 |
DOIs | |
State | Published - 2004 |
Event | Proceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, United States Duration: Apr 18 2004 → Apr 21 2004 |
Other
Other | Proceedings of the International Symposium on Physical Design, ISPD 2004 |
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Country/Territory | United States |
City | Phoenix, AZ |
Period | 4/18/04 → 4/21/04 |
Keywords
- Congestion prediction
- Technology mapping