The objective of the via minimization is to assign wire segments into different layers to minimize the number of vias required. Several algorithms have been proposed for the Constrained Via Minimization (CVM) problem where the topology of the given layout is fixed. In a CVM problem, some vias may be "essential" to the given layout. That is, they have to be selected and cannot be replaced by other vias. In this paper we present a procedure to find most of the essential vias. This procedure can be used as a preprocessor for the algorithms for CVM problems. Experimental results show that the procedure is efficient and can identify most of essential vias.
|Original language||English (US)|
|Title of host publication||Proceedings of the 23rd ACM/IEEE Design Automation Conference, DAC 1986|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|State||Published - Jul 2 1986|
|Event||23rd ACM/IEEE Design Automation Conference, DAC 1986 - Las Vegas, United States|
Duration: Jun 29 1986 → Jul 2 1986
|Name||Proceedings - Design Automation Conference|
|Other||23rd ACM/IEEE Design Automation Conference, DAC 1986|
|Period||6/29/86 → 7/2/86|
Bibliographical noteFunding Information:
*This work was supported in part by NSF Grant DCR-8405498, by a grant from CDC/IIoneywell/Sperry, and by a grant from MEIS.