A reconfigurable stochastic architecture for highly reliable computing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations

Abstract

Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that operates on probabilistic signals, and so can cope with errors and uncertainty. Techniques for probabilistic analysis are well established. We advocate a strategy for synthesis. In this paper, we present a reconfigurable architecture that implements the computation of arbitrary continuous functions with stochastic logic. We analyze the sources of error: approximation, quantization, and random fluctuations. We demonstrate the effectiveness of our method on a collection of benchmarks for image processing. Synthesis trials show that our stochastic architecture requires less area than conventional hardware implementations. It achieves a large speed up compared to software conventional implementations. Most importantly, it is much more tolerant of soft errors (bit flips) than these deterministic implementations.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI
Pages315-320
Number of pages6
DOIs
StatePublished - 2009
Event19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA, United States
Duration: May 10 2009May 12 2009

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
CountryUnited States
CityBoston, MA
Period5/10/095/12/09

Keywords

  • Reconfigurable architecture
  • Reliable computing
  • Stochastic logic

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