A reduced-complexity architecture for LDPC layered decoding schemes

Sangmin Kim; Gerald E. Sobelman; Hanho Lee

doi:10.1109/TVLSI.2010.2043965

A reduced-complexity architecture for LDPC layered decoding schemes

Sangmin Kim, Gerald E. Sobelman, Hanho Lee

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

37 Scopus citations

Abstract

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

Original language	English (US)
Article number	5439945
Pages (from-to)	1099-1103
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2010.2043965
State	Published - Jun 2011

Bibliographical note

Funding Information:
Manuscript received August 15, 2009; revised November 18, 2009. First published March 29, 2010; current version published May 25, 2011. This work was supported in part by the Electronics and Telecommunications Research Institute (ETRI).

Keywords

Decoding
field-programmable gate array (FPGA)
forward error correction
low density parity check (LDPC)

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abstract = "A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.",

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A reduced-complexity architecture for LDPC layered decoding schemes

Abstract

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Keywords

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