A retargetable and accurate methodology for logic-IP-internal electromigration assessment

Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.

Original languageEnglish (US)
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages346-351
Number of pages6
ISBN (Electronic)9781479977925
DOIs
StatePublished - Mar 11 2015
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: Jan 19 2015Jan 22 2015

Publication series

Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/TerritoryJapan
CityChiba
Period1/19/151/22/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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