A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.
|Original language||English (US)|
|Title of host publication||20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|State||Published - Mar 11 2015|
|Event||2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan|
Duration: Jan 19 2015 → Jan 22 2015
|Name||20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015|
|Other||2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015|
|Period||1/19/15 → 1/22/15|
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© 2015 IEEE.