A retargetable and accurate methodology for logic-IP-internal electromigration assessment

Palkesh Jain; Sachin S. Sapatnekar; Jordi Cortadella

doi:10.1109/ASPDAC.2015.7059029

A retargetable and accurate methodology for logic-IP-internal electromigration assessment

Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.

Original language	English (US)
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	346-351
Number of pages	6
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7059029
State	Published - Mar 11 2015
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: Jan 19 2015 → Jan 22 2015

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	1/19/15 → 1/22/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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10.1109/ASPDAC.2015.7059029

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Jain, P., Sapatnekar, S. S., & Cortadella, J. (2015). A retargetable and accurate methodology for logic-IP-internal electromigration assessment. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 346-351). Article 7059029 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059029

A retargetable and accurate methodology for logic-IP-internal electromigration assessment. / Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella, Jordi.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 346-351 7059029 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jain, P, Sapatnekar, SS & Cortadella, J 2015, A retargetable and accurate methodology for logic-IP-internal electromigration assessment. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059029, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 346-351, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 1/19/15. https://doi.org/10.1109/ASPDAC.2015.7059029

Jain P, Sapatnekar SS, Cortadella J. A retargetable and accurate methodology for logic-IP-internal electromigration assessment. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 346-351. 7059029. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7059029

Jain, Palkesh ; Sapatnekar, Sachin S. ; Cortadella, Jordi. / A retargetable and accurate methodology for logic-IP-internal electromigration assessment. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 346-351 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

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A retargetable and accurate methodology for logic-IP-internal electromigration assessment

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