A mixed-signal time-based 65-nm application specific integrated circuit is developed for solving shortest-path problems in 3-D. Previous path planning ASICs have been restricted to 2-D maps due to computational complexity or physical architecture limitations. Our time-based, asynchronous, one-shot architecture has been coupled with a novel dual axis interleaving strategy to solve the multidimensional shortest path problem in a simple, energy efficient manner. Additional features include circuit-based solutions for obstacle blockage avoidance and gravity. The efficacy of the proposed ASIC is evaluated on a drone navigation application, 3-D Voronoi diagrams, and a physical optics experiment. The chip is twice as energy efficient as prior 2-D work while containing 5\times more vertices and 7.5\times additional edge connections.
Bibliographical noteFunding Information:
Manuscript received October 23, 2019; revised January 19, 2020 and April 2, 2020; accepted April 30, 2020. Date of publication May 21, 2020; date of current version June 12, 2020. This work was supported in part by the National Science Foundation under Award CCF-1763761. This article was approved by Associate Editor Lluca Benini. This work was supported in part by the National Science Foundation under Award CCF-1763761. (Corresponding author: Luke R. Everson.) The authors are with the Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MI 55455 USA (e-mail: email@example.com). Digital Object Identifier 10.1109/LSSC.2020.2995051 Fig. 1. Prior work of path planning chips targeted at 3-D, but falls short in that they do not fully compute the third dimensions due to computational limitations  or limited connectivity .
© 2018 IEEE.
- A algorithm
- graph computing
- single-source shortest path
- time-domain computing
- time-to-digital converter