Approximate computing is a promising approach for low power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy configurable adder designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of these designs include error detection and correction circuitry, which further increases area. In this work, we investigate a simple accuracy configurable adder design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. Simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% lower area. Moreover, we propose a delay-adaptive self-configuration technique to further improve accuracy-delay-power tradeoff.
|Original language||English (US)|
|Title of host publication||ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Aug 11 2017|
|Event||22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China|
Duration: Jul 24 2017 → Jul 26 2017
|Name||Proceedings of the International Symposium on Low Power Electronics and Design|
|Other||22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017|
|Country/Territory||Taiwan, Province of China|
|Period||7/24/17 → 7/26/17|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This project is partially supported by NSF(CCF-1255193, CCF-1525749 and CCF-1525925). The authors would like to thank Dr. Duncan M. Walker from Texas A&M University for helpful discussions.