Abstract
In this paper we present the first fully integrated analog LDO (low dropout regulator) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. In order to realize the gate drive at sub-0.5V supply voltages, we introduce a negative charge pump based adaptive offset before the pass FET which provides gate-source headroom at input operation voltages normally reserved for digital LDOs. The smart-adaptive-negative offset voltage follows a 0.5-0.5xVdd scheme to accommodate a wide range of input voltages while providing the necessary extra gate drive for the power FET at low inputs. The 32 phase charge pump runs at a frequency of 3GHz with a ripple of ∼ 3mV. The prototype was fabricated in TSMC's 65nm GP CMOS.
| Original language | English (US) |
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| Title of host publication | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 269-272 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538631782 |
| DOIs | |
| State | Published - Dec 26 2017 |
| Event | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Seoul, Korea, Republic of Duration: Nov 6 2017 → Nov 8 2017 |
Publication series
| Name | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Proceedings |
|---|---|
| Volume | 2017-January |
Conference
| Conference | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 |
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| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 11/6/17 → 11/8/17 |
Bibliographical note
Funding Information:This work was supported by SRC/TxACE task ID 2712.008. The authors thank Rakesh Palani for useful discussions.
Publisher Copyright:
© 2017 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.