A voltage scalable 0.26 V, 64 kb 8T SRAM with vjnin lowering techniques and deep sleep mode

Tae Hyoung Kim, Jason Liu, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

98 Scopus citations

Abstract

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.

Original languageEnglish (US)
Article number4982884
Pages (from-to)1785-1795
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number6
DOIs
StatePublished - Jun 1 2009

Keywords

  • Bitline leakage compensation
  • Floating bitlines
  • Low-voltage SRAM design
  • Minimum operation voltage
  • Sleep mode

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