A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode

Wei Zhang, Ki Chul Chun, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing standby power at times when only a fraction of the entire memory is utilized. Measurement results from a 64 kb eDRAM test chip in 65 nm CMOS demonstrate the effectiveness of the proposed circuit techniques

Original languageEnglish (US)
Article number6522141
Pages (from-to)2030-2038
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number8
DOIs
StatePublished - Jun 6 2013

Keywords

  • Dual row access
  • embedded DRAM
  • gain cell
  • local sense amplifier
  • low power
  • write-back-free read

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