Abstract
A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing standby power at times when only a fraction of the entire memory is utilized. Measurement results from a 64 kb eDRAM test chip in 65 nm CMOS demonstrate the effectiveness of the proposed circuit techniques
Original language | English (US) |
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Article number | 6522141 |
Pages (from-to) | 2030-2038 |
Number of pages | 9 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 60 |
Issue number | 8 |
DOIs | |
State | Published - 2013 |
Keywords
- Dual row access
- embedded DRAM
- gain cell
- local sense amplifier
- low power
- write-back-free read