Accurate estimation of global buffer delay within a floorplan

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, C. N. Sze

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer insertion solution unrealizable. The theory of [12] is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution. Potential applications include wire planning, timing analysis during floorplanning or global routing. Our experiments show that our approach accurately predicts delay when compared to constructing an realizable buffer insertion with multiple buffer types.

Original languageEnglish (US)
Title of host publicationICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages706-711
Number of pages6
DOIs
StatePublished - 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

OtherICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Country/TerritoryUnited States
CitySan Jose, CA
Period11/7/0411/11/04

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