AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption

Wenfeng Zhao; Yajun Ha; Massimo Alioto

doi:10.1109/ISCAS.2015.7169155

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption

Wenfeng Zhao, Yajun Ha, Massimo Alioto

Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

30 Scopus citations

Abstract

Lightweight encryption circuits are crucial to ensure adequate information security in emerging millimeter-scale platforms for the Internet of Things, which are required to deliver moderately high throughput under stringent area and energy budgets. This requires the adoption of specialized AES accelerators, as they offer orders of magnitude energy improvements over microcontroller-based implementations. In this paper, we present the architectural exploration of lightweight AES accelerators with the goal of minimizing the energy consumption. Also, the lower bound of the number of cycles per encryption in lightweight AES designs is estimated as a function of the number of available S-boxes. Combined with sub-/near-threshold circuit techniques, we present a low-cost ultra energy-efficient AES encryption core for cubic-millimeter platforms. Our test chip achieves high energy efficiency of 0.83 pJ/bit at 0.32V, which outperforms the state-of-the-art low-cost AES designs by 7×.

Original language	English (US)
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2349-2352
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169155
State	Published - Jul 27 2015
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	5/24/15 → 5/27/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Advanced Encryption Standard
energy-efficient architecture
sub-/near-threshold operation
ultra-low energy

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISCAS.2015.7169155

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Zhao, W., Ha, Y., & Alioto, M. (2015). AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2349-2352). Article 7169155 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169155

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. / Zhao, Wenfeng; Ha, Yajun; Alioto, Massimo.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2349-2352 7169155 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhao, W, Ha, Y & Alioto, M 2015, AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169155, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 2349-2352, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7169155

Zhao W, Ha Y, Alioto M. AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2349-2352. 7169155. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2015.7169155

Zhao, Wenfeng ; Ha, Yajun ; Alioto, Massimo. / AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2349-2352 (Proceedings - IEEE International Symposium on Circuits and Systems).

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AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption

Abstract

Publication series

Other

Bibliographical note

Keywords

UN SDGs

Access

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