TY - JOUR
T1 - ALIGN
T2 - A System for Automating Analog Layout
AU - Dhar, Tonmoy
AU - Kunal, Kishor
AU - Li, Yaguang
AU - Madhusudan, Meghna
AU - Poojary, Jitesh
AU - Sharma, Arvind K.
AU - Xu, Wenbin
AU - Burns, Steven M.
AU - Harjani, Ramesh
AU - Hu, Jiang
AU - Kirkpatrick, Desmond A.
AU - Mukherjee, Parijat
AU - Yaldiz, Soner
AU - Sapatnekar, Sachin S.
N1 - Funding Information:
This work was supported in part by the DARPA IDEA program under SPAWAR Contract N660011824048.
PY - 2021/4
Y1 - 2021/4
N2 - This article describes a correct by construction approach to synthesize electrically and designs compliant design. By taking advantage of layout hierarchies the researchers are able to apply this to an interesting class of circuits. The philosophy of ALIGN is to compositionally synthesize the layout by first identifying layout hierarchies in the netlist, then generating correct-by-construction layouts at the lowest level of the hierarchy, and finally assembling blocks at each level of hierarchy during placement and routing. A key step in ALIGN is to identify these hierarchies to recognize the building blocks of the design. In doing so, ALIGN mimics the human designer, who identifies known blocks, lays them out, and then builds the overall layout hierarchically.
AB - This article describes a correct by construction approach to synthesize electrically and designs compliant design. By taking advantage of layout hierarchies the researchers are able to apply this to an interesting class of circuits. The philosophy of ALIGN is to compositionally synthesize the layout by first identifying layout hierarchies in the netlist, then generating correct-by-construction layouts at the lowest level of the hierarchy, and finally assembling blocks at each level of hierarchy during placement and routing. A key step in ALIGN is to identify these hierarchies to recognize the building blocks of the design. In doing so, ALIGN mimics the human designer, who identifies known blocks, lays them out, and then builds the overall layout hierarchically.
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U2 - 10.1109/MDAT.2020.3042177
DO - 10.1109/MDAT.2020.3042177
M3 - Article
AN - SCOPUS:85097959100
SN - 2168-2356
VL - 38
SP - 8
EP - 18
JO - IEEE Design and Test
JF - IEEE Design and Test
IS - 2
M1 - 9279310
ER -