ALIGN: A System for Automating Analog Layout

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

This article describes a correct by construction approach to synthesize electrically and designs compliant design. By taking advantage of layout hierarchies the researchers are able to apply this to an interesting class of circuits. The philosophy of ALIGN is to compositionally synthesize the layout by first identifying layout hierarchies in the netlist, then generating correct-by-construction layouts at the lowest level of the hierarchy, and finally assembling blocks at each level of hierarchy during placement and routing. A key step in ALIGN is to identify these hierarchies to recognize the building blocks of the design. In doing so, ALIGN mimics the human designer, who identifies known blocks, lays them out, and then builds the overall layout hierarchically.

Original languageEnglish (US)
Article number9279310
Pages (from-to)8-18
Number of pages11
JournalIEEE Design and Test
Volume38
Issue number2
DOIs
StatePublished - Apr 2021

Bibliographical note

Funding Information:
This work was supported in part by the DARPA IDEA program under SPAWAR Contract N660011824048.

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