An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs

Pulkit Jain, John Keane, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A comprehensive Chip LIfetime Predictor (CLIP) macro for automatically characterizing gate dielectric failure reduces the stress time and silicon area by a factor proportional to the number of FETs to be tested. A flexible DUT cell that can be stressed in isolation without thicker tox FETs to 4 times supply voltage, enables accurate lifetime prediction under different ON and OFF state dielectric breakdown modes for both low voltage core and high voltage IO devices.

Original languageEnglish (US)
Title of host publication2012 Proceedings of the European Solid-State Device Research Conference, ESSDERC 2012
Pages262-265
Number of pages4
DOIs
StatePublished - Dec 11 2012
Event42nd European Solid-State Device Research Conference, ESSDERC 2012 - Bordeaux, France
Duration: Sep 17 2012Sep 21 2012

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other42nd European Solid-State Device Research Conference, ESSDERC 2012
CountryFrance
CityBordeaux
Period9/17/129/21/12

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