TY - GEN
T1 - An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm
AU - Meng, Qingrui
AU - Harjani, Ramesh
N1 - Publisher Copyright:
© 2016 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/10/18
Y1 - 2016/10/18
N2 - This paper presents a novel four-channel, four-beam receiver core based on a FFT core that is easily extended to a larger number of beams. This architecture is particulary well suited for MIMO systems where multiple beams are used for increased throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial filtering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial filtering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0.65mm2 excluding pads and test circuits.
AB - This paper presents a novel four-channel, four-beam receiver core based on a FFT core that is easily extended to a larger number of beams. This architecture is particulary well suited for MIMO systems where multiple beams are used for increased throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial filtering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial filtering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0.65mm2 excluding pads and test circuits.
KW - Butler matrix
KW - FFT
KW - beamforming
KW - multi-beam
KW - multiple-input-multiple-output (MIMO)
KW - phased array
KW - spatial filter
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U2 - 10.1109/ESSCIRC.2016.7598316
DO - 10.1109/ESSCIRC.2016.7598316
M3 - Conference contribution
AN - SCOPUS:84994403395
T3 - European Solid-State Circuits Conference
SP - 359
EP - 362
BT - ESSCIRC 2016
PB - IEEE Computer Society
T2 - 42nd European Solid-State Circuits Conference, ESSCIRC 2016
Y2 - 12 September 2016 through 15 September 2016
ER -