TY - GEN
T1 - An efficient multi-protocol RFID interrogator baseband processor based on a reconfigurable architecture
AU - Zhao, Shuang
AU - Lu, Wenqing
AU - Lu, Chao
AU - Zhou, Xiaofang
AU - Zhou, Dian
AU - Sobelman, Gerald E
PY - 2008/9/22
Y1 - 2008/9/22
N2 -
With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multi-protocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm
2
in a UMC 0.18μm CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area.
AB -
With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multi-protocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm
2
in a UMC 0.18μm CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area.
KW - ISO18000
KW - Multi-protocol
KW - RFID
KW - Reconfigurable baseband processor
UR - http://www.scopus.com/inward/record.url?scp=51849165532&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51849165532&partnerID=8YFLogxK
U2 - 10.1109/ICESS.2008.61
DO - 10.1109/ICESS.2008.61
M3 - Conference contribution
AN - SCOPUS:51849165532
SN - 9780769532875
T3 - Proceedings of The International Conference on Embedded Software and Systems, ICESS 2008
SP - 264
EP - 270
BT - Proceedings of The International Conference on Embedded Software and Systems, ICESS 2008q
T2 - 2008 International Conference on Embedded Software and Systems, ICESS-08
Y2 - 29 July 2008 through 31 July 2008
ER -