Abstract
Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay-optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.
Original language | English (US) |
---|---|
Pages | 137-144 |
Number of pages | 8 |
DOIs | |
State | Published - 2005 |
Event | 2005 International Symposium on Physical Design, ISPD'05 - San Francisco, CA, United States Duration: Apr 3 2005 → Apr 6 2005 |
Other
Other | 2005 International Symposium on Physical Design, ISPD'05 |
---|---|
Country/Territory | United States |
City | San Francisco, CA |
Period | 4/3/05 → 4/6/05 |
Keywords
- Logic synthesis
- Routing congestion
- Technology mapping