TY - GEN
T1 - An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams
AU - Li, Bingzhe
AU - Najafi, M. Hassan
AU - Lilja, David J.
N1 - Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2015/9/8
Y1 - 2015/9/8
N2 - Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.
AB - Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.
UR - http://www.scopus.com/inward/record.url?scp=84955591146&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84955591146&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2015.7245709
DO - 10.1109/ASAP.2015.7245709
M3 - Conference contribution
AN - SCOPUS:84955591146
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 68
EP - 69
BT - Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
Y2 - 27 July 2015 through 29 July 2015
ER -