An investigation of performance limits of conventional and tunneling graphene-based transistors

R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani

Research output: Contribution to journalArticlepeer-review

12 Scopus citations


In this paper we perform a simulation study on the limits of graphene-nanoribbon field-effect transistors (GNR-FETs) for post-CMOS digital applications. Both conventional and tunneling FET architectures are considered. Simulations of conventional narrow GNR-FETs confirm the high potential of these devices, but highlight at the same time OFF-state leakage problems due to various tunneling mechanisms, which become more severe as the width is made larger and require a careful device optimization. Such OFF-state problems are partially solved by the tunneling FETs, which allow subthreshold slopes better than 60 mV/dec, at the price of a reduced ON-current. The importance of a very good control on edge roughness is highlighted by means of a direct simulation of devices with non-ideal edges.

Original languageEnglish (US)
Pages (from-to)441-450
Number of pages10
JournalJournal of Computational Electronics
Issue number3-4
StatePublished - Dec 2009

Bibliographical note

Funding Information:
Acknowledgements This work has been supported by the EU FP7 IST Project GRAND (Contract n. 215752) via the IU.NET Consortium.


  • Carbon electronics
  • Graphene nanoribbons
  • Nanoelectronic devices
  • Tunneling FET


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