Negative bias temperature instability (NBTI) has been considered as a main reliability issue in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has raised minimum operating voltage (VMIN) over time. This paper explains an SRAM reliability test macro designed in a 1.2 V, 65 nm CMOS process technology for statistical measurements of VMIN degradation coming from NBTI. An automated test program efficiently collects statistical VMIN data and reduces test time. The proposed test structure enables VMIN degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The VMIN dependency on initial device mismatch and stored data is also presented. The measured time to cell data flip affected by NBTI shows the similar trend of NBTI following a power-law dependency on stress time.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Mar 2012|
- Circuit reliability
- Negative bias temperature instability (NBTI)
- Static random access memory (SRAM)