Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Masoud Zabihi, Arvind K. Sharma, Meghna G. Mankalale, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Salonik Resch, Ulya R. Karpuzcu, Jian Ping Wang, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

Original languageEnglish (US)
Article number9056847
Pages (from-to)71-79
Number of pages9
JournalIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Volume6
Issue number1
DOIs
StatePublished - Jun 2020

Bibliographical note

Funding Information:
Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA CORRESPONDING AUTHOR: M. ZABIHI (zabih003@umn.edu) This work was supported in part by NSF SPXunder Award CCF-1725420. This article has supplementary downloadable material available at http://ieeexplore.ieee.org, provided by the authors.

Publisher Copyright:
© 2014 IEEE.

Keywords

  • In-memory computing
  • spin-transfer torque computational random access memory (STT-CRAM)
  • spintronics

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