Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Masoud Zabihi; Arvind K. Sharma; Meghna G. Mankalale; Zamshed Iqbal Chowdhury; Zhengyang Zhao; Salonik Resch; Ulya R. Karpuzcu; Jian Ping Wang; Sachin S. Sapatnekar

doi:10.1109/JXCDC.2020.2985314

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Masoud Zabihi, Arvind K. Sharma, Meghna G. Mankalale, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Salonik Resch, Ulya R. Karpuzcu, Jian Ping Wang, Sachin S. Sapatnekar

Electrical and Computer Engineering

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Abstract

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

Original language	English (US)
Article number	9056847
Pages (from-to)	71-79
Number of pages	9
Journal	IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Volume	6
Issue number	1
DOIs	https://doi.org/10.1109/JXCDC.2020.2985314
State	Published - Jun 2020

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

In-memory computing
spin-transfer torque computational random access memory (STT-CRAM)
spintronics

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Zabihi, M., Sharma, A. K., Mankalale, M. G., Chowdhury, Z. I., Zhao, Z., Resch, S., Karpuzcu, U. R., Wang, J. P., & Sapatnekar, S. S. (2020). Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 6(1), 71-79. Article 9056847. https://doi.org/10.1109/JXCDC.2020.2985314

Zabihi, M, Sharma, AK, Mankalale, MG, Chowdhury, ZI, Zhao, Z, Resch, S, Karpuzcu, UR , Wang, JP & Sapatnekar, SS 2020, 'Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform', IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, 9056847, pp. 71-79. https://doi.org/10.1109/JXCDC.2020.2985314

@article{fb0e321774134dfbbb611012bdc53753,

title = "Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform",

abstract = "This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.",

keywords = "In-memory computing, spin-transfer torque computational random access memory (STT-CRAM), spintronics",

author = "Masoud Zabihi and Sharma, {Arvind K.} and Mankalale, {Meghna G.} and Chowdhury, {Zamshed Iqbal} and Zhengyang Zhao and Salonik Resch and Karpuzcu, {Ulya R.} and Wang, {Jian Ping} and Sapatnekar, {Sachin S.}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

year = "2020",

month = jun,

doi = "10.1109/JXCDC.2020.2985314",

language = "English (US)",

volume = "6",

pages = "71--79",

journal = "IEEE Journal on Exploratory Solid-State Computational Devices and Circuits",

issn = "2329-9231",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

AU - Zabihi, Masoud

AU - Sharma, Arvind K.

AU - Mankalale, Meghna G.

AU - Chowdhury, Zamshed Iqbal

AU - Zhao, Zhengyang

AU - Resch, Salonik

AU - Karpuzcu, Ulya R.

AU - Wang, Jian Ping

AU - Sapatnekar, Sachin S.

PY - 2020/6

Y1 - 2020/6

N2 - This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

AB - This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

KW - In-memory computing

KW - spin-transfer torque computational random access memory (STT-CRAM)

KW - spintronics

UR - http://www.scopus.com/inward/record.url?scp=85092779977&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85092779977&partnerID=8YFLogxK

U2 - 10.1109/JXCDC.2020.2985314

DO - 10.1109/JXCDC.2020.2985314

M3 - Article

AN - SCOPUS:85092779977

SN - 2329-9231

VL - 6

SP - 71

EP - 79

JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

IS - 1

M1 - 9056847

ER -

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

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