Application-specific 3D network-on-chip design using simulated allocation

Pingqiang Zhou; Ping Hung Yuh; Sachin S. Sapatnekar

doi:10.1109/ASPDAC.2010.5419830

Application-specific 3D network-on-chip design using simulated allocation

Pingqiang Zhou, Ping Hung Yuh, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Scopus citations

Abstract

Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

Original language	English (US)
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages	517-522
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419830
State	Published - 2010
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China Duration: Jan 18 2010 → Jan 21 2010

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Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country/Territory	Taiwan, Province of China
City	Taipei
Period	1/18/10 → 1/21/10

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Application-specific 3D network-on-chip design using simulated allocation. / Zhou, Pingqiang; Yuh, Ping Hung; Sapatnekar, Sachin S.
2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 517-522 5419830 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhou, P, Yuh, PH & Sapatnekar, SS 2010, Application-specific 3D network-on-chip design using simulated allocation. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419830, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 517-522, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 1/18/10. https://doi.org/10.1109/ASPDAC.2010.5419830

@inproceedings{76b023c6fa904ed8930df188f2df0f31,

title = "Application-specific 3D network-on-chip design using simulated allocation",

abstract = "Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).",

author = "Pingqiang Zhou and Yuh, {Ping Hung} and Sapatnekar, {Sachin S.}",

year = "2010",

doi = "10.1109/ASPDAC.2010.5419830",

language = "English (US)",

isbn = "9781424457656",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "517--522",

booktitle = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010",

note = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 18-01-2010 Through 21-01-2010",

}

TY - GEN

T1 - Application-specific 3D network-on-chip design using simulated allocation

AU - Zhou, Pingqiang

AU - Yuh, Ping Hung

AU - Sapatnekar, Sachin S.

PY - 2010

Y1 - 2010

N2 - Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

AB - Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

UR - http://www.scopus.com/inward/record.url?scp=77951241020&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951241020&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2010.5419830

DO - 10.1109/ASPDAC.2010.5419830

M3 - Conference contribution

AN - SCOPUS:77951241020

SN - 9781424457656

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 517

EP - 522

BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

Y2 - 18 January 2010 through 21 January 2010

ER -

Application-specific 3D network-on-chip design using simulated allocation

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