Abstract
This paper presents a performance comparison of new authenticated encryption (AE) algorithms which are aimed at providing better security and resource efficiency compared to existing standards. Specifically, these algorithms improve the security of existing AE standards by providing a critical property termed nonce-misuse resistance. This paper addresses algorithm to architectural mappings of several candidates from the ongoing Competition for AE: Security, Applicability, and Robustness as well as a submission from the Crypto Forum Research Group. Implementations of the architectures on both field-programmable gate arrays and application-specific integrated circuits platforms are provided and compared with the architecture of a popular standard: Advanced Encryption Standard in Galois Counter mode (AES-GCM). Optimizations that are applicable to AE, in general, and nonce-misuse-resistant architectures, in particular, are presented. A hardware-software codesign approach to optimization is also discussed. The implementations via proposed optimizations demonstrate that new AE algorithms can provide comparable performance as standard AES-GCM while enhancing security and resource utilization for specific use-case scenarios.
Original language | English (US) |
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Article number | 8648246 |
Pages (from-to) | 1053-1066 |
Number of pages | 14 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 27 |
Issue number | 5 |
DOIs | |
State | Published - May 2019 |
Bibliographical note
Publisher Copyright:© 1993-2012 IEEE.
Keywords
- Advanced encryption standard in galois counter mode (aes-gcm)
- Aes-gcm-synthetic IV (sIV)
- Applicability
- Authenticated encryption (ae)
- Competition for ae: Security
- Deoxys
- Nonce-misuse resistance
- Pipelineable on-line encryption with authentication tag (poet)
- Primate-ape
- Robustness (caesar) competition