TY - JOUR
T1 - Architectures for multi-gigabit wire-linked clock and data recovery
AU - Hsieh, Ming Ta
AU - Sobelman, Gerald E.
PY - 2008/12
Y1 - 2008/12
N2 - Clock and data recovery (CDR) architectures used in high-speed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized.
AB - Clock and data recovery (CDR) architectures used in high-speed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized.
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U2 - 10.1109/MCAS.2008.930152
DO - 10.1109/MCAS.2008.930152
M3 - Article
AN - SCOPUS:57649118674
SN - 1531-636X
VL - 8
SP - 45
EP - 57
JO - IEEE Circuits and Systems Magazine
JF - IEEE Circuits and Systems Magazine
IS - 4
ER -