Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

Qianying Tang, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper presents a novel method for characterizing the impact of random telegraph noise (RTN) on logic timing margin under sub-0.5V supply voltages. The proposed dual ring oscillator array test structure improves the frequency measurement resolutions of the tested-and-proven beat frequency detection (BFD) technique by pairing a ROSC from one array with a ROSC from a second array having a similar frequency. Detailed circuit level RTN data was collected from a 32nm HKMG test chip, including voltage stress results. Measured data confirms that the proposed dual-array technique is effective in collecting high quality RTN statistics at sub-0.5V. The impact of RTN on logic timing margin is estimated based on the measured frequency data.

Original languageEnglish (US)
Title of host publication2015 IEEE International Electron Devices Meeting, IEDM 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages20.7.1-20.7.4
ISBN (Electronic)9781467398930
DOIs
StatePublished - Feb 16 2015
Event61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States
Duration: Dec 7 2015Dec 9 2015

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2016-February
ISSN (Print)0163-1918

Other

Other61st IEEE International Electron Devices Meeting, IEDM 2015
CountryUnited States
CityWashington
Period12/7/1512/9/15

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