Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

Qianying Tang; Chris H. Kim

doi:10.1109/IEDM.2015.7409745

Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

Qianying Tang, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents a novel method for characterizing the impact of random telegraph noise (RTN) on logic timing margin under sub-0.5V supply voltages. The proposed dual ring oscillator array test structure improves the frequency measurement resolutions of the tested-and-proven beat frequency detection (BFD) technique by pairing a ROSC from one array with a ROSC from a second array having a similar frequency. Detailed circuit level RTN data was collected from a 32nm HKMG test chip, including voltage stress results. Measured data confirms that the proposed dual-array technique is effective in collecting high quality RTN statistics at sub-0.5V. The impact of RTN on logic timing margin is estimated based on the measured frequency data.

Original language	English (US)
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	20.7.1-20.7.4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409745
State	Published - Feb 16 2015
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: Dec 7 2015 → Dec 9 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Other

Other	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	12/7/15 → 12/9/15

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10.1109/IEDM.2015.7409745

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Tang, Q., & Kim, C. H. (2015). Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 20.7.1-20.7.4). Article 7409745 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409745

Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array. / Tang, Qianying; Kim, Chris H.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 20.7.1-20.7.4 7409745 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tang, Q & Kim, CH 2015, Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409745, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 20.7.1-20.7.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 12/7/15. https://doi.org/10.1109/IEDM.2015.7409745

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Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

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