Automatic generation of control circuits in pipelined DSP architectures

Ching Yi Wang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Novel algorithms for synthesis of control circuits in pipelined signal processing architectures are presented. The algorithms generate appropriate latching and switching of intermediate signals for a functionally correct operation. Sufficient theory of pipelining is developed to ensure iteration independence of the registers used in control circuits of the dedicated architectures. The interprocessor control circuits are being incorporated into CAD systems for dedicated designs. Algorithms for automatic generation of all control circuits for a specified sequencing and scheduling of operations, for single and multiple clock, and for single and multiple implementation styles are presented.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherPubl by IEEE
Pages324-327
Number of pages4
ISBN (Print)O81862079X
StatePublished - Sep 1 1990
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: Sep 17 1990Sep 19 1990

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period9/17/909/19/90

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