@inproceedings{f0f2ae752ff84d189227bb5f06a17281,
title = "Automatic generation of control circuits in pipelined DSP architectures",
abstract = "Novel algorithms for synthesis of control circuits in pipelined signal processing architectures are presented. The algorithms generate appropriate latching and switching of intermediate signals for a functionally correct operation. Sufficient theory of pipelining is developed to ensure iteration independence of the registers used in control circuits of the dedicated architectures. The interprocessor control circuits are being incorporated into CAD systems for dedicated designs. Algorithms for automatic generation of all control circuits for a specified sequencing and scheduling of operations, for single and multiple clock, and for single and multiple implementation styles are presented.",
author = "Wang, {Ching Yi} and Parhi, {Keshab K.}",
year = "1990",
month = sep,
day = "1",
language = "English (US)",
isbn = "O81862079X",
series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
publisher = "Publ by IEEE",
pages = "324--327",
booktitle = "Proceedings - IEEE International Conference on Computer Design",
note = "Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",
}