Buffering global interconnects in structured ASIC design

Tianpei Zhang, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This paper proposes a novel and accurate statistical estimation technique for distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the buffer distribution estimation is accurate and economic, and that a uniform buffer distribution can maintain a high degree of regularity in design and shows a good timing performance, comparable with nonuniform buffer distribution.

Original languageEnglish (US)
Pages (from-to)171-182
Number of pages12
JournalIntegration, the VLSI Journal
Volume41
Issue number2
DOIs
StatePublished - Feb 1 2008

Keywords

  • Buffer insertion
  • Interconnect
  • Physical design
  • Rent's rule
  • Structured ASIC

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